1. Field of the Invention
The present invention relates to a data processing device with an instruction translator for translating instructions not native to a certain processor into instructions native to the same processor, and can rapidly execute a program including a processing routine formed of nonnative instructions and a processing routine formed of native instructions in a mixed fashion. The invention also relates to a memory interface device for such a data processing device.
2. Description of the Background Art
There is a close relationship between a processor architecture and a system of instructions that can be executed on such a processor. If the instruction set is updated in accordance with advance of the processor architecture, those program codes written for the old processors designed in accordance with the old instruction sets will usually be impossible to execute. What is most important is how the programs implemented in accordance with the old instruction set will be effectively inherited. For this purpose, many techniques have been developed for executing the programs, which were written for old processors designed in accordance with the old instruction set, by new processors having a certain instruction set.
One of the typical conventional schemes for executing the program written for the old processor on a new processor, is to provide hardware of the new processor with a function of the old processor. Referring to FIG. 1, a conventional data processing device for performing such a method includes a processor 1 provided with a multifunction instruction decoder 5, which has functions of decoding both the instructions for the old processor and the instructions for the new processor, and an arithmetic portion 6 having a function of executing these instructions. The data processing device further includes a bus 4 connected to processor 1 as well as a data memory 2 and an instruction memory 3, which are connected to bus 4.
Instruction memory 3 holds both the instructions of the old processor and the instructions of the new processor. Multifunction instruction decoder 5 decodes instructions read from instruction memory 3 and transferred to processor 1 via bus 4. Multifunction instruction decoder 5 has the function of decoding both the instructions for the new processor and the instructions for the old processor. Execution portion 6 executes the decoded instruction. Data memory 2 can be accessed from both the instruction for the new processor and the instruction for the old processor.
Examples of the technique, in which the function of hardware of the old processor is given to the hardware of new processor, have been described in various books and magazines primarily for the developers, and reference can be made on them for more information.
In addition, the conventional methods for executing the programs for the old processor on the new processor includes one wherein the software for the old processor is first translated into software for the new processor and then executed, and one wherein the operations of instructions for the old processor are emulated by the software running on the new processor. These methods are likewise described in various books and magazines primarily for developers, and reference can be made on them for more information.
In some other cases, it may also be effective to execute the program written for a certain instruction set by the processor designed in accordance with another instruction set. For example, the program size can be reduced by defining a subset of a certain instruction set and writing a program in the subset. JAVA™ language is designed such that programs are written for an instruction set prescribed for a virtual processor, and a different kinds of processors execute the same program thus written by using instruction sets of the each processor. Therefore, the program written in the JAVA language can be commonly executed by multiple kinds of processors of different instruction sets.
There have been proposed many methods, in which the subjects of instruction sets are prepared for reducing the program size, and both the instructions of the non-reduced instruction set and the instructions of the reduced instruction set are decoded by a multifunction instruction decoder of a processor. For example, reference may be made to “Thumb Squeezes ARM Code Size (New Core Module Provides Optimizes Second Instruction Set)” by James L. Turley (Micro Processor Report, Vol. 9, No. 4, pp. 1 and 6-9, Mar. 27, 1995).
However, the conventional methods described above all suffer from the following problems.
If the function of executing the program written in the plurality of instruction sets are given to hardware of the processor, the hardware becomes complicated, and have increased sizes. For adding or changing an instruction set to be executed, the whole hardware must be redesigned, and it is difficult to deal with such addition and change with flexibility.
The following problem arises when changing or translating the program by the software. For translating the program itself, a memory of a large capacity is additionally required for holding the translated program. This increases costs of the memory and therefore the data processing device. In the case of emulating the operation of instructions with the instructions of another instruction set, it is naturally necessary to emulate the operation results, and further it is necessary to emulate values of program counters and, if necessary, flags. For this reason, it is necessary to replace the operation of one instruction with many instructions of another set. This significantly lowers the operation speed.